`timescale 1ns/1ps
 module tb_top;
    reg clk;
    reg rst;
    reg enable;
    wire [7:0] segment;
    wire [5:0] seg_cs;
    wire cout;
top inst(.clk(clk),
         .rst(rst),
         .enable(enable),
         .seg_cs(seg_cs),
         .segment(segment),
         .cout(cout));
initial
    begin
        clk=0;
        rst=0;
        enable=0;
        #100 rst=1;
        #100 enable=1;
    end
    always #1 clk=~clk;
endmodule
